How can future hardware make our software more secure?

Frustrated with security issues in your code?

Find adding security too costly and slow? 

Hate bugs that find you and not vice versa?

Are you a software engineer who’s interested in trialling and challenging a new technique that stops buffer overflows and other memory-safety issues — even in C or C++?

Come to this future tech talks and networking event to discover:

• Cambridge University’s new CHERI architecture: Capability Hardware Enhanced RISC Instructions.
• Why Arm partnered with University of Cambridge to develop prototype silicon.
• How you can use this prototype — the Arm Morello Board — to find bugs and memory safety issues.
• How you can get hold of a Morello board plus £15,000 funding to trial the Morello prototype architecture in your organisation.

During the event you’ll have the opportunity to talk to the designers and ask questions about this new technology.

4.30 pm Registration opens

5.00 pm Event starts

5.10 pm Prof. Simon Moore from University of Cambridge explaining the CHERI concept and its development journey.

5.30 pm Mark Inskip, Arm’s Morello Program Director will talk us through Arm’s Morello project and explain why Arm is now developing prototype hardware.

5.50 pm Katy Ho, Head of Innovation at Digital Catapult will talk about the different ways you and your organisation can get involved through the Technology Access Programme.

6.00 pm Q&A and discussion with the presenters, hosted by Matt Evans, Computer Architecture & Security Advisor at Digital Catapult.

6.15 Networking with food and drinks in the atrium

7.30 Event close

* Spaces are limited – register now *